1. Field of the Invention
The present invention relates to a method of filling a bit line contact via, and more specifically to a method of forming a conductive layer in the bit line contact via.
2. Description of the Related Art
As the integrity of integrated circuits increases, the size of semiconductor device is reduced. A dynamic random access memory (DRAM) device for example, has design rule for 64 MB DRAM of 0.3 μm or less, with design rule of 128 MB and 256 MB as low as 0.2 μm or less.
In a bit line contact structure, for example, when the line width is reduced to approximately 0.11 μm, the width of a drain region exposed by a bit line contact via is also reduced to approximately 0.038 μm or less. When forming a conductive layer as bit line contact (CB) in the bit line contact via, either CB opening or word line-bit line short occur frequently, resulting in device failure, thereby negatively affecting the yield and cost of the process.
FIGS. 1A through 1F are cross-sections illustrating these problems in the conventional method of filling a bit line contact via.
In FIG. 1A, first, a substrate 100, such as single crystalline silicon, having a transistor structure, is provided. The substrate 100 has a gate electrode 120 protruding from an active surface of substrate 100. A drain region 112 and source region 114 are disposed on the active surface respectively on two sides of the gate electrode 120. Gate electrode 120 is a word line, having a multi-level structure as needed. For example, gate electrode 120 in FIG. 1A can have gate dielectric layer 121, polycrystalline silicon layer 122 and metal silicide layer 123 as conductive layers, and hard mask layer 124 sequentially from the active surface of substrate 100. Gate electrode 120 further has a spacer 125 on the sidewall, resulting in width of exposed drain region 112 between two neighboring gate electrodes 120 as large as approximately 0.038 μm or less when design rule is reduced to approximately 0.11 μm.
In FIG. 1B, a dielectric layer 130 and patterned resist layer 191 are sequentially formed on substrate 100. The patterned resist layer 191 has an opening 191a exposing a part of dielectric layer 130, a predetermined position of a subsequent bit line contact via. The dielectric is usually about 0.3 μm to about 1.0 μm thick.
The subsequent steps include removing the exposed dielectric layer 130 in order to form the bit line contact via exposing drain region 112, and filling a metal layer in the bit line contact via as a bit line contact. FIGS. 1C and 1D show CB opening and FIGS. 1E and 1F show word line-bit line short occurring in the aforementioned steps.
In FIG. 1C, dielectric layer 130 exposed by opening 191a is removed by anisotropic etching, using patterned resist layer 191 as an etching mask, in order to form a via 131, as a bit line contact via, exposing drain region 112. Then, patterned resist layer 191 is removed. As mentioned above, width of the exposed drain region 112 is approximately 0.038 μm or less, resulting in via 131 being extremely deep relative to the thickness of dielectric layer 130, about 0.3 μm to about 1.0 μm as disclosed. The etching reaction slows as dielectric layer 130 at the bottom of via 131 is etched, resulting in remaining dielectric layer 130 not being etched completely, at the bottom of via 131, thereby failing to expose drain region 112.
In FIG. 1D, a barrier layer 140 and conductive layer 150 are formed sequentially in via 131 as a bit line contact. The bit line contact fails to electrically connect to drain region 112 resulting from the remaining dielectric layer 130 between the barrier layer 140 and drain region 112. Thus, CB opening occurs.
In FIG. 1E, after the step shown in FIG. 1B, dielectric layer 130 exposed by opening 191a is removed by anisotropic etching, using patterned resist layer 191 as an etching mask, in order to form a via 131′, as a bit line contact via, exposing drain region 112. Then, patterned resist layer 191 is removed. In order to completely remove the dielectric 130 at the bottom of via 131′, over-etching is performed on dielectric 130. As shown in FIG. 1A or 1B, hard mask layer 124 and spacer 125 protect gate electrode 120 from electrically connecting to the subsequently formed bit line contact or bit line. Further, dielectric layer 130 is etched with high etch selectivity, of, for example, about 10, with respect to hard mask layer 124 and spacer 125 in order to prevent exposing the conductive layers, polycrystalline silicon layer 122 and metal silicide layer 123, during etching of dielectric 130, when dielectric layer 130 is silicon oxide and both the hard mask layer 124 and spacer 125 are silicon nitride. When over-etching is performed to force etching of the dielectric 130 at the bottom of via 131′, a part of hard mask layer 124 and spacer 125 may be removed, thereby exposing the metal silicide layer 123, and more seriously, polycrystalline silicon layer 122 may be exposed.
In FIG. 1F, a barrier layer 140 and conductive layer 150 are formed sequentially in via 131′ as a bit line contact. The exposed metal silicide layer 123 electrically connects to the bit line contact. Thus, word line-bit line short occurs.